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POWER

POWER

POWER is a RISC CPU architecture designed by IBM. The name is a backronym for Performance Optimization With Enhanced RISC. The POWER series microprocessors are used as the main CPU in many of IBM's servers, minicomputers, workstations, and supercomputers. The POWER architecture was used to develop (and remains very similar to) the PowerPC architecture, used in later Apple Macintosh computers, some IBM workstations, as well as a number of embedded applications. IBM also is encouraging other developers and manufacturers to use the POWER architecture or any other derivative of it through the [http://www.Power.org/ Power.org] community.

R.A.S. Technologies

Grid-Computing

- 1989 ESCON

Research that brings the POWER

1974 Research Project “801”

Starting with a design objective of creating a large telephone-switching-network with a potential capacity to deal with at least 300 calls per/second. And a projected use of 20,000 instructions for each call while maintaining a real-time response, a safety margin of at least 12MIPS was deemed necessary. Even though this requirement had been extremely ambitious at this time, the switching-network would need only to perform I/O, branches, add register-register, move to register/memory, and have little need for floating-point/complex instructions. By 1975 without an actual prototype just design rules and simulations, the telephone project was canceled. But from the estimates from the simulations this looked like it could be a very promising microprocessor, so work continued at Thomas J, Watson Research Center building #801.
- "801" design v1.x
- "801" design v2.x
- 1987 John Cocke wins "Turing Award" for the creation of RISC The defining principle of RISC are (1) (2). By the name “RISC” you might be lead to believe that there are less instructions then compared to a “CISC Architecture”, and those a the perceived benefits of RISC over CISC. The benefits lie in Reducing the Instruction Set Complexity so you end up with more pieces that are needed to do the same thing, and parallel execution.

1982 Research Project “Cheetah”

For 2-years at the Watson Research Center the supercaler limits of the “801” design were explored. Such as the feasibility of implementing the “801” design using multiple functional units to improve performance, similar to what had been done in the IBM System/360 Model 91and the CDC 6600 both of which had been bases on CISC designs though. To determine if a RISC machine could maintain multiple instructions per cycle, or what design changes need to be made to the “801” design to allow for a multiple-execution-unit “801” design. To increase performance “Cheetah” had separate branch, fixed-point, and floating-point execution units. Many changes were made to the “801” design to allow for a multiple-execution-unit design. Originally planned to be manufactured using bibolar-ECL technology, but by 1984 CMOS afforded an increase in the level of circuit integration while improving transistor-logic performance.

1985 Research Project “AMERICA”

1988 Research Project “Belatrix”

- 1990 POWER1
- 1993 POWER2
- 1996 P2SC
- 1997 POWER3

1991 Research Project “AMAZON”

- (RS64(Muskie))
- (RS64/RCS(Cobra))Single chip-design
- 1994 PowerPC620
- 1997 RS64(Apache)
- 1998 RS64II(Northstar)
- 1999 RS64III(Pulsar)
- 2000 RS64IV(I-Star)
- 2001 RS64V(S-star)
- 2003 PowerPC970
- 2004 PowerPC970fx
- 2005 PowerPC970MP

1991 Project PowerPC

- 1993 PowerPC601
- 1993 PowerPC603
- 1994 PowerPC604

1996 Research Project “GigaProcessor”

- 2001 POWER4
- 2004 POWER5
- POWER6
- POWER7

1999 Project GEKKO

- 2002 GEKKO
- 2006 Revolution

2000 Research Project “CELL”

- 2005 CELL

2000 Project FPGA-PowerPC

2001 Research Project CRS-1

2004 Project Xbox360

- 2005 (Xenon)

The architecture

Apple Macintosh The POWER design is descended directly from the earlier IBM 801 CPU, widely considered to be the first true RISC chip design. The 801 was used in a number of applications inside IBM hardware, but did not become publicly known until they released the poorly-performing IBM PC/RT in the mid-1980s. At about the same time the PC/RT was being released, IBM started the America Project, to design the most powerful CPU on the market. They were interested primarily in fixing two problems in the 801 design: #the 801 required all instructions to complete in one clock cycle, which eliminated floating point instructions #although the decoder was pipelined as a side effect of these single-cycle operations, they didn't use superscalar effects Floating point became a focus for the America Project, and IBM was able to use new algorithms developed in the early 1980s that could support 64-bit double-precision multiplies and divides in a single cycle. The FPU portion of the design was separate from the instruction decoder and integer parts, allowing the decoder to send instructions to both the FPU and ALU (integer) execution units at the same time. IBM complemented this with a complex instruction decoder which could be fetching one instruction, decoding another, and sending one to the ALU and FPU at the same time, resulting in one of the first superscalar CPU designs in use. The system used thirty-two 32-bit integer registers and another thirty-two 64-bit floating point registers, each in their own unit. The branch unit also included a number of "private" registers for its own use, including the program counter. The 801 was a simple design, and an overcorrection to its simplicity resulted in the POWER design being more complex than most RISC CPUs. For instance, the POWER (and PowerPC) instruction set includes over 100 op-codes of variable length, many of which are variations on others. This compares (for instance) with the ARM which has only 34 instructions. Another interesting feature of the architecture is a virtual address system which maps all addresses into a 52-bit space. In this way applications can share memory in a "flat" 32-bit space, and all of the programs can have different blocks of 32-bits each.

Implementations

The first POWER1 CPUs consisted of three chips; branch, integer and floating point. These were wired together on a largish motherboard to produce a single system. POWER1 was used primarily in the RS/6000 series of workstations. POWER2 was a product-improved POWER1 and was the longest-lived of the POWER series, released in 1993 and still used five years later. It added a second floating-point unit, 256 KiB of cache and 128-bit floating point math. POWER3 followed in 1998, moving to a full 64-bit implementation, while remaining completely compatible with the POWER instruction set. This had been one of the goals of the PowerPC project and the POWER3 was the first of the IBM processors to take advantage of it. It also added a third ALU and a second instruction decoder, for a total of eight functional units. The POWER4 series places two complete CPU cores (otherwise similar to the POWER3) on a single chip, speeds it up, and adds high-speed connections to up to three additional pairs of POWER4 CPUs. They can be placed together on a motherboard to produce an 8-CPU SMP building block. When processing requires high throughput instead of high code complexity, one of a pair of cores can be turned off so that the remaining cores have the entire bus and L3 cache to themselves. The POWER4, even in single form, is considered by many to be the most powerful CPU available. In 2003, IBM introduced a single CPU core version of the POWER4 called the PowerPC 970. It was employed in the newest generation of Apple desktop computers (that is, the G5). IBM rolled out the POWER5 processor in 2004. The 1.9 GHz version posted the highest uniprocessor SPECfp score of any shipping chip. The POWER5 powers the i5 and p5 eServers. Improvements in the POWER5 over the POWER4 include: a larger L2 cache, a memory controller on the chip, simultaneous multithreading which appears to the operating system as multiple CPUs, advanced power management, dedicated single-tasking mode, Hypervisor (virtualization technology), and eFuse (hardware re-routing around faults). Ravi Arimilli, IBM's chief microprocessor designer has said: "The POWER5 chip is more of a midrange design that can drive up to the high end and then down to things like blades." IBM servers built with the POWER5 processor offer virtualization features: logical partitioning and micro partitioning. Up to ten LPARs (logical partitions) can be created for each CPU, the biggest 64-Way system can run 256 independent operating systems. Memory, CPU-Power and I/O can be dynamically moved between partitions. See also Linux on Power. As of 2005, development of POWER6 and POWER7 variants is underway.

Derivative CPUs

POWER7 POWER7 The PowerPC was essentially a POWER1 CPU with some of the more basic instructions emulated in microcode, using a bus interface based on the Motorola 88000 design. This allowed IBM to use the CPU in a number of workstation machines, changing only the motherboard. Since then the PowerPC and POWER architectures have diverged somewhat, but remain compatible at the instruction level. The IBM RS64 family of processors is based on PowerPC (and thus POWER) and has been used in the RS/6000 and AS/400 product lines. It is optimized for commercial workloads, and does not have the floating point power expected in the POWER line. It is now mostly replaced by the POWER4. The Cell processor is also derived from the POWER architecture, resembling a POWER3-like core with limited floating point performance, coupled to eight independent vector processors. Intended to power the Sony PlayStation 3, the Cell appears to dramatically outperform -- albeit only at very specific tasks -- almost all desktop processors on the market today, and has generated intense interest in the industry. The Xbox 360, the next generation of Microsoft gaming console will use a triple-core PowerPC processor clocked at 3.2 GHz[http://www.xbox.com/en-US/xbox360/factsheet.htm].

Who Licenses PowerPC

Motorola, Sony, CISCO, Toshiba, Samsung, AMCC, Microsoft, PA-Semi, HCL, Xilinx, Altera... and others.

Industry AWARDS

- 2005 IBM wins its eighth "National Medal of Technlology", for over 40 years of innovation. Given to American Companies who are leading innovators by The President of the United States.
- 2004
- 2003
- 2002
- 2001
- 2000
- 1999
- 1998
- 1997
- 1996
- 1993

External links

- [http://www-1.ibm.com/technology/power/ IBM's Power Architecture page]
- [http://www.ibm.com/developerworks/power IBM Power Architecture weekly magazine]
- [http://www.power.org/ Power.org]
- [http://www.the400squadron.com/amug/200406/NotPowerPC.htm When Is PowerPC Not PowerPC? (History of the POWER Architecture by Frank Soltis)]
- [http://www.pegasosforum.de/ Pegasos Forum] - German Community of the Pegasos PowerPC Project Power Power Category:POWER architecture ja:POWER

RISC

:This article is about computer architecture; for use of the acronym in biology, see RNA-induced silencing complex. Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. The most common RISC microprocessors are ARM, DEC Alpha, PA-RISC, SPARC, MIPS, and IBM PowerPC. The idea was inspired by the discovery that many of the features that were included in traditional CPU designs to facilitate coding were being ignored by the programs that were running on them. Also these more complex features took several processor cycles to be performed. In addition, the speed of the CPU in relation to the memory it accessed was increasing. This led to a number of techniques to streamline processing within the CPU, while at the same time attempting to reduce the total number of memory accesses.

RISC design philosophy

In the late 1970s research at IBM (and similar projects elsewhere) demonstrated that the majority of these "orthogonal" addressing modes were ignored by most programs. This was a side effect of the increasing use of compilers to generate the programs, as opposed to writing them in assembly language. The compilers in use at the time only had a limited ability to take advantage of the features provided by CISC CPUs; this was largely a result of the difficulty of writing a compiler. The market was clearly moving to even wider use of compilers, diluting the usefulness of these orthogonal modes even more. Another discovery was that since these operations were rarely used, in fact they tended to be slower than a number of smaller operations doing the same thing. This seeming paradox was a side effect of the time spent designing the CPUs, designers simply did not have time to tune every possible instruction, and instead tuned only the most used ones. One famous example of this was the VAX's INDEX instruction, which ran slower than a loop implementing the same code. At about the same time CPUs started to run even faster than the memory they talked to. Even in the late 1970s it was apparent that this disparity was going to continue to grow for at least the next decade, by which time the CPU would be tens to hundreds of times faster than the memory. It became apparent that more registers (and later caches) would be needed to support these higher operating frequencies. These additional registers and cache memories would require sizeable chip or board areas that could be made available if the complexity of the CPU was reduced. Yet another part of RISC design came from practical measurements on real-world programs. Andrew Tanenbaum summed up many of these, demonstrating that most processors were vastly overdesigned. For instance, he showed that 98% of all the constants in a program would fit in 13 bits, yet almost every CPU design dedicated some multiple of 8 bits to storing them, typically 8, 16 or 32, one entire word. Taking this fact into account suggests that a machine should allow for constants to be stored in unused bits of the instruction itself, decreasing the number of memory accesses. Instead of loading up numbers from memory or registers, they would be "right there" when the CPU needed them, and therefore much faster. However this required the instruction itself to be very small, otherwise there would not be enough room left over in the 32-bits to hold reasonably sized constants. It was the small number of addressing modes and commands that resulted in the term Reduced Instruction Set. This is not an accurate terminology, as RISC designs often have huge command sets of their own. The real difference is the philosophy of doing everything in registers and loading and saving the data to and from them. This is why the design is more properly referred to as load-store. Over time the older design technique became known as Complex Instruction Set Computer, or CISC, although this was largely to give them a different name for comparison purposes. Thus the RISC philosophy was to make smaller instructions, implying fewer of them, and thus the name "reduced instruction set". Code was implemented as a series of these simple instructions, instead of a single complex instruction that had the same result. This had the side effect of leaving more room in the instruction to carry data with it, meaning that there was less need to use registers or memory. At the same time the memory interface was considerably simpler, allowing it to be tuned. However RISC also had its drawbacks. Since a series of instructions is needed to complete even simple tasks, the total number of instructions read from memory is larger, and therefore takes longer. At the time it was not clear whether or not there would be a net gain in performance due to this limitation, and there was an almost continual battle in the press and design world about the RISC concepts.

Pre-RISC design philosophy

In the early days of the computer industry, compiler technology did not exist. Programming was done in either machine code or assembly language. To make programming easier, computer architects created more and more complex instructions which were direct representations of high level functions of high level programming languages. The attitude at the time was that hardware design was easier than compiler design, so the complexity went into the hardware. Another force that encouraged complex instructions was the lack of large memories. Since memories were small, it was advantageous for the density of information held in computer programs to be very high. When every byte of memory was precious, for example one's entire system only had a few kilobytes of storage, it moved the industry to such features as highly encoded instructions, instructions which could be variable sized, instructions which did multiple operations and instructions which did both data movement and data calculation. At that time, such instruction packing issues were of higher priority than the ease of decoding such instructions. Memory was not only small, but rather slow since they were implemented using magnetic technology at the time. That was another reason to keep the density of information very high. By having dense information packing, one could decrease the frequency when one had to access this slow resource. CPUs had few registers for two reasons:
- bits in internal CPU registers are always more expensive than bits in external memory. The available level of silicon integration of the day meant large register sets would have been burdensome to the chip area or board areas available.
- Having a large number of registers would have required a large number of instruction bits (using precious RAM) to be used as register specifiers. For the above reasons, CPU designers tried to make instructions that would do as much work as possible. This led to one instruction that would do all of the work in a single instruction: load up the two numbers to be added, add them, and then store the result back directly to memory. Another version would read the two numbers from memory, but store the result in a register. Another version would read one from memory and the other from a register and store to memory again. And so on. This processor design philosophy eventually became known as Complex Instruction Set Computer (CISC). The general goal at the time was to provide every possible addressing mode for every instruction, a principle known as "orthogonality." This led to some complexity on the CPU, but in theory each possible command could be tuned individually, making the design faster than if the programmer used simpler commands. The ultimate expression of this sort of design can be seen at two ends of the power spectrum, the 6502 at one end, and the VAX at the other. The $25 single-chip 6502 effectively had only a single register, and by careful tuning of the memory interface it was still able to outperform designs running at much higher speeds (like the 4 MHz Zilog Z80). The VAX was a minicomputer whose initial implementation required 3 racks of equipment for a single cpu, and was notable for the amazing variety of memory access styles it supported, and the fact that every one of them was available for every instruction.

Meanwhile...

While the RISC philosophy was coming into its own, new ideas about how to dramatically increase performance of the CPUs were starting to develop. In the early 1980s it was thought that existing design was reaching theoretical limits. Future improvements in speed would be primarily through improved semiconductor "process", that is, smaller features (transistors and wires) on the chip. The complexity of the chip would remain largely the same, but the smaller size would allow it to run at higher clock rates. A considerable amount of effort was put into designing chips for parallel computing, with built-in communications links. Instead of making faster chips, a large number of chips would be used, dividing up problems among them. However history has shown that the original fears were not valid, and there were a number of ideas that dramatically improved performance in the late 1980s. One idea was to include a pipeline which would break down instructions into steps, and work on one step of several different instructions at the same time. A normal processor might read an instruction, decode it, fetch the memory the instruction asked for, perform the operation, and then write the results back out. The key to pipelining is the observation that the processor can start reading the next instruction as soon as it finishes reading the last, meaning that there are now two instructions being worked on (one is being read, the next is being decoded), and after another cycle there will be three. While no single instruction is completed any faster, the next instruction would complete right after the previous one. The illusion was of a much faster system, and more efficient utilization of processor resources. Yet another solution was to use several processing elements inside the processor and run them in parallel. Instead of working on one instruction to add two numbers, these superscalar processors would look at the next instruction in the pipeline and attempt to run it at the same time in an identical unit. However, this can be difficult to do, as many instructions in computing depend on the results of some other instruction. Both of these techniques relied on increasing speed by adding complexity to the basic layout of the CPU, as opposed to the instructions running on them. With chip space being a finite quantity, in order to include these features something else would have to be removed to make room. RISC was tailor-made to take advantage of these techniques, because the core logic of a RISC CPU was considerably simpler than in CISC designs. Although the first RISC designs had marginal performance, they were able to quickly add these new design features and by the late 1980s they were significantly outperforming their CISC counterparts. In time this would be addressed as process improved to the point where all of this could be added to a CISC design and still fit on a single chip, but this took most of the late-80s and early 90s. The long and short of it is that for any given level of general performance, a RISC chip will typically have many fewer transistors dedicated to the core logic. This allows the designers considerable flexibility; they can, for instance:
- increase the size of the register set
- implement measures to increase internal parallelism
- increase the size of caches
- add other functionality, like I/O and timers for microcontrollers
- add vector (SIMD) processors like AltiVec and Streaming SIMD Extensions (SSE)
- build the chips on older fabrication lines, which would otherwise go unused
- do nothing; offer the chip for battery-constrained or size-limited applications Features which are generally found in RISC designs are:
- uniform instruction encoding (for example the op-code is always in the same bit position in each instruction, which is always one word long), which allows faster decoding;
- a homogenous register set, allowing any register to be used in any context and simplifying compiler design (although there are almost always separate integer and floating point register files);
- simple addressing modes (complex addressing modes are replaced by sequences of simple arithmetic instructions);
- few data types supported in hardware (for example, some CISC machines had instructions for dealing with byte strings. Others had support for polynomials and complex numbers. Such instructions are unlikely to be found on a RISC machine). RISC designs are also more likely to feature a Harvard memory model, where the instruction stream and the data stream are conceptually separated; this means that modifying the addresses where code is held might not have any effect on the instructions executed by the processor (because the CPU has a separate instruction and data cache), at least until a special synchronization instruction is issued. On the upside, this allows both caches to be accessed simultaneously, which can often improve performance. Many of these early RISC designs also shared a not-so-nice feature, the branch delay slot. A branch delay slot is an instruction space immediately following a jump or branch. The instruction in this space is executed whether or not the branch is taken (in other words the effect of the branch is delayed). This instruction keeps the ALU of the CPU busy for the extra time normally needed to perform a branch. Nowadays the branch delay slot is considered an unfortunate side effect of a particular strategy for implementing some RISC designs, and modern RISC designs generally do away with it (such as PowerPC, more recent versions of SPARC, and MIPS).

Early RISC

The first system that would today be known as RISC was not at the time; it was the CDC 6600 supercomputer, designed in 1964 by Jim Thornton and Seymour Cray. Thornton and Cray designed it as a number-crunching CPU (with 74 op-codes, compared with a 8086's 400) plus 12 simple computers called "peripheral processors" to handle I/O (most of the operating system was in one of these). The CDC 6600 had a load/store architecture with only two addressing modes. There were eleven pipelined functional units for arithmetic and logic, plus five load units and two store units (the memory had multiple banks so all load/store units could operate at the same time). The basic clock cycle/instruction issue rate was 10 times faster than the memory access time. Another early load/store machine was the Data General Nova minicomputer, designed in 1968. The most public RISC designs, however, were the results of university research programs run with funding from the DARPA VLSI Program. The VLSI Program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics. UC Berkeley's RISC project started in 1980 under the direction of David Patterson, based on gaining performance through the use of pipelining and an aggressive use of registers known as register windows. In a normal CPU one has a small number of registers, and a program can use any register at any time. In a CPU with register windows, there are a huge number of registers, 128, but programs can only use a small number of them, 8, at any one time. A program that limits itself to 8 registers per procedure can make very fast procedure calls: The call, and the return, simply move the window to the set of 8 registers used by that procedure. (On a normal CPU, most calls "flush" the contents of the registers to RAM to clear enough working space for the subroutine, and the return "restores" those values). The RISC project delivered the RISC-I processor in 1982. Consisting of only 44,420 transistors (compared with averages of about 100,000 in newer CISC designs of the era) RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design. They followed this up with the 40,760 transistor, 39 instruction RISC-II in 1983, which ran over three times as fast as RISC-I. At about the same time, John L. Hennessy started a similar project called MIPS at Stanford University in 1981. MIPS focussed almost entirely on the pipeline, making sure it could be run as "full" as possible. Although pipelining was already in use in other designs, several features of the MIPS chip made its pipeline far faster. The most important, and perhaps annoying, of these features was the demand that all instructions be able to complete in one cycle. This demand allowed the pipeline to be run at much higher speeds (there was no need for induced delays) and is responsible for much of the processor's speed. However, it also had the negative side effect of eliminating many potentially useful instructions, like a multiply or a divide. The earliest attempt to make a chip-based RISC CPU was a project at IBM which started in 1975, predating both of the projects above. Named after the building where the project ran, the work led to the IBM 801 CPU family which was used widely inside IBM hardware. The 801 was eventually produced in a single-chip form as the ROMP in 1981, which stood for Research (Office Products Division) Mini Processor. As the name implies, this CPU was designed for "mini" tasks, and when IBM released the IBM RT-PC based on the design in 1986, the performance was not acceptable. Nevertheless the 801 inspired several research projects, including new ones at IBM that would eventually lead to their POWER system. In the early years, the RISC efforts were well known, but largely confined to the university labs that had created them. The Berkeley effort became so well known that it eventually became the name for the entire concept. Many in the computer industry criticized that the performance benefits were unlikely to translate into real-world settings due to the decreased memory efficiency of multiple instructions, and that that was the reason no one was using them. But starting in 1986, all of the RISC research projects started delivering products. In fact, almost all modern RISC processors are direct copies of the RISC-II design.

Later RISC

Berkeley's research was not directly commercialized, but the RISC-II design was used by Sun Microsystems to develop the SPARC, by Pyramid Technology to develop their line of mid-range multi-processor machines, and by almost every other company a few years later. It was Sun's use of a RISC chip in their new machines that demonstrated that RISC's benefits were real, and their machines quickly outpaced the competition and essentially took over the entire workstation market. John Hennessy left Stanford (temporarily) to commercialize the MIPS design, starting the company known as MIPS Computer Systems Their first design was a second-generation MIPS chip known as the R2000. MIPS designs went on to become one of the most used RISC chips when they were included in the PlayStation and Nintendo 64 game consoles. Today they are one of the most common embedded processors in use for high-end applications. IBM learned from the RT-PC failure and would go on to design the RS/6000 based on their new POWER architecture. They then moved their existing AS/400 mainframes to POWER chips, and found much to their surprise that even the very complex instruction set ran considerably faster. The result was the new iSeries. POWER would also find itself moving "down" in scale to produce the PowerPC design, which eliminated many of the "IBM only" instructions and created a single-chip implementation. Today the PowerPC is used in all Apple Macintosh machines, as well as being one of the most commonly used CPUs for automotive applications (some cars have over 10 of them inside). On June 6, 2005 Apple decided to switch to using Intel processors, with the first Apple-i386 based on the Pentium M to be sold sometime near the beginning of 2006. Almost all other vendors quickly joined. From the UK similar research efforts resulted in the INMOS Transputer, the Acorn Archimedes and the Advanced RISC Machine line, which is a huge success today. Companies with existing CISC designs also quickly joined the revolution. Intel released the i860 and i960 by the late 1980s, although they were not very successful. Motorola built a new design called the 88000 in homage to their famed CISC 68000, but it saw almost no use and they eventually abandoned it and joined IBM to produce the PowerPC. AMD released their 29000 which would go on to become the most popular RISC design of the early 1990s. Today RISC CPUs (and microcontrollers) represent the vast majority of all CPUs in use. The RISC design technique offers power in even small sizes, and thus has come to completely dominate the market for low-power "embedded" CPUs. Embedded CPUs are by far the largest market for processors: while a family may own one or two PCs, their car(s), cell phones, and other devices may contain a total of dozens of embedded processors. RISC had also completely taken over the market for larger workstations for much of the 90s. After the release of the Sun SPARCstation the other vendors rushed to compete with RISC based solutions of their own. Even the mainframe world is now completely RISC based. However, despite many successes, RISC has made few inroads into the desktop PC and commodity server markets, where Intel's x86 platform remains the dominant processor architecture (Intel is facing increased competition from AMD, but even AMD's processors implement the x86 platform, or a 64-bit superset known as x86-64). There are three main reasons for this. One, the very large base of proprietary PC applications are written for x86, whereas no RISC platform has a similar installed base, and this meant PC users were locked into the x86 despite a lack of performance. The second is that, although RISC was indeed able to scale up in performance quite quickly and cheaply, Intel took advantage of its large market by spending enormous amounts of money on processor development. Intel could spend many times as much as any RISC manufacturer on improvements in design and manufacturing, making up for inherent flaws in the basic x86 architecture. The third reason is that Intel designers realized that they could apply RISC design philosophies and practices to their architecture. For example, the P6 core of the PentiumPro processor and its successors has special functional units which expand, or "crack", the majority of the CISC instructions into multiple simpler RISC operations. Internally, processors using the P6 core are RISC machines that emulate a CISC architecture. Consumers are interested in speed, cost per chip, and compatibility with existing software rather than the cost of development of new chips. This has led to an interesting chain of events. As the complexity of developing more and more advanced CPUs increases, the cost of both development and fabrication of high-end CPUs has exploded. The cost gains RISC gave to the CPU designer are now dwarfed by the high costs of developing any modern CPU, and today only the biggest chip makers are capable of making high performing CPUs. The end result is that virtually all RISC platforms with the exception of IBM's POWER/PowerPC have greatly shrunk in scale of development of high performing CPUs (like SPARC and MIPS) or even abandoned (like Alpha and PA-RISC) during the 00s. As of 2004, x86 chips are the fastest CPUs in SPECint displacing all RISC CPUs, and the fastest CPU in SPECfp is the IBM Power 5 processor. Still, RISC designs have led to a number of successful platforms and architectures, some of the larger ones being:
- MIPS's MIPS line, found in most SGI computers and the PlayStation and Nintendo 64 game consoles
- IBM's POWER series, used in all of their SuperComputers/mainframes
- Freescale (formerly Motorola SPS) and IBM's PowerPC (a subset of the POWER architecture) used in Microsoft's Xbox 360, Nintendo's Revolution and Sony's Playstation 3 game consoles, and, until recently, all Apple Macintosh computers
- Sun's SPARC and UltraSPARC, found in all of their later machines
- Hewlett-Packard's PA-RISC HP/PA
- DEC Alpha
- ARM — Palm, Inc. originally used the (CISC) Motorola 680x0 processors in its early PDAs, but now uses (RISC) ARM processors in its latest PDAs; Nintendo uses an ARM7 CPU in the Game Boy Advance and Nintendo DS handheld game systems. The small Korean company Gamepark also markets the GP32, which uses the ARM9 CPU.

Alternative term

Because RISC instruction sets have tended grow in size over the years, some people have started to use the term "load-store" to describe RISC chips (since this is the key element to all RISC designs). Instead of the CPU itself handling all sorts of addressing modes, a load-store architecture uses a separate unit that is dedicated to handling very simple forms of load and store operations.

International Business Machines

:Big Blue redirects here. For the movie, see The Big Blue. International Business Machines Corporation (IBM, or colloquially, Big Blue) (incorporated June 15, 1911, in operation since 1888) is headquartered in Armonk, NY, USA. The company manufactures and sells computer hardware, software, and services. With over 330,000 employees worldwide and revenues of $96 billion (figures from 2004), IBM is the largest information technology company in the world, and one of the few with a continuous history dating back to the 19th century. It has engineers and consultants in over 170 countries and development laboratories located all over the world, in all segments of computer science and information technology; some of them are pioneers in areas ranging from mainframe computers to nanotechnology. In recent years, services and consulting revenues have been larger than those from manufacturing. Samuel J. Palmisano was elected CEO on January 29, 2002 after having led IBM's Global Services, and helping it to become a business with a $100 billion in backlog in 2004 [http://www.ibm.com/ibm/sjp/bio.shtml]. In 2002 the company strengthened its business advisory capabilities by acquiring the consulting arm of professional services firm PricewaterhouseCoopers. The consulting arm was previously known as Monday. The company is increasingly focused on business solution driven consulting, services and software, with emphasis also on high value chips and hardware technologies; as of 2005 it employs about 195,000 technical professionals. That total includes about 350 Distinguished Engineers and 60 IBM Fellows, its most senior engineers. IBM Research has eight laboratories, all located in the Northern Hemisphere, with five of those locations outside of the United States. IBM employees have won five Nobel Prizes. In the USA, they have earned four Turing Awards, five National Medals of Technology, and five National Medals of Science, and outside the USA, many equivalents.

Current business activities

In 2002, IBM announced the beginning of a $10 billion program to research and implement the infrastructure technology necessary to be able to provide supercomputer-level resources "on demand" to all businesses as a metered utility. This program will be implemented over the coming years. In recent years IBM has steadily increased its patent portfolio, which is valuable for cross-licensing with other companies. In every year from 1993 until 2004, IBM has been granted significantly more U.S. patents than any other company. That twelve-year period has resulted in over 29,000 patents for which IBM is the primary assignee. [http://www.research.ibm.com/resources/news/20000111_patents99.shtml] Protection of the company's intellectual property has grown into a business in its own right, generating over $10 billion dollars [http://www.industryweek.com/CurrentArticles/asp/articles.asp?ArticleID=1400] to the bottom line for the company during this period. [http://www.forbes.com/2003/08/07/cx_ld_0807ibm_print.html], [http://www.inc.com/articles/legal/ip/patents/23293.html] A 2003 Forbes article quotes the head of IBM Research, who suggested a $1 billion in profit just for the research staff; however, they probably generate the bulk of new inventions in the company. In 2005, IBM sold its PC division to China-based Lenovo. As part of the agreement, Lenovo moved its headquarters to New York State. IBM owns a significant stake (about 19%) in Lenovo. Starting from the date of the acquisition, Lenovo is permitted five years' use of the IBM and "Think" trademarks.

Culture

IBM has often been described as having a sales-centric or a sales-oriented business culture. Traditionally, many of its executives and general managers would be chosen from its sales force. In addition, middle and top management would often be enlisted to give direct support to salesmen in the process of making sales to important customers. For most of the 20th century, a blue suit, white shirt and dark tie was the public uniform of IBM employees. But by the 1990s, IBM relaxed these codes; the dress and behavior of its employees does not differ appreciably from that of their counterparts in large technology companies. In 2003, IBM embarked on an ambitious project to rewrite company values using its "Jam" technology -- Intranet-based online discussions on key business issues for a limited time, involving more than 50,000 employees over 3 days in this case. Jam technology includes sophisticated text analysis software (eClassifier) to mine online comments for themes, and Jams have now been used six times internally at IBM. As a result of the 2003 Jam, the company values were updated to reflect three modern business, marketplace and employee views: "Dedication to every client's success", "Innovation that matters - for our company and for the world", "Trust and personal responsibility in all relationships". In 2004, another Jam was conducted in which more than 52,000 employees exchanged best practices for 72 hours. This event was focused on finding actionable ideas to support implementation of the values identified previously. A new post-Jam Ratings event was developed to allow IBMers to select key ideas that support the values. (For further information, see Harvard Business Review, December 2004, interview with IBM Chairman Sam Palmisano.) IBM's culture has been recently influenced by the open source movement. The company invests billions of dollars in services and software based on Linux. This includes over 300 Linux kernel developers. IBM's open source involvement has not been trouble-free, however; see SCO v. IBM.

Diversity and workforce issues

IBM's efforts to promote workforce diversity and equal opportunity date back at least to World War I, when the company hired disabled veterans. More recently, IBM received a 100% rating on the Corporate Equality Index released by the Human Rights Campaign starting in 2003, the second year of the report. IBM is the only technology company ranked in [http://www.workingwoman.com/top10.html Working Mother Magazine's Top 10] for 2004. The company has traditionally resisted labor union organizing, although unions represent some IBM workers outside the United States. [http://www.allianceibm.org Alliance@IBM], part of the Communications Workers of America, is trying to organize IBM in the U.S. In the 1990s, two major pension program changes, including a conversion to a cash balance plan, resulted in an employee class action lawsuit alleging age discrimination. IBM employees won the lawsuit and arrived at a partial settlement, although appeals are still underway. Historically IBM has had a good reputation of long term staff retention with few large scale layoffs. In more recent years there have been a number of broad sweeping cuts to the workforce as IBM attempts to adapt to changing market conditions and a declining profit base. After posting weaker than expected revenues in the first quarter of 2005, IBM eliminated 14,500 positions from its workforce, predominantly in Europe. There has also been a steadily increasing movement of labour to cheap offshore countries such as India. On October 10, 2005, IBM became the first major company in the world to formally commit to not using genetic information in its employment decisions. This came just a few months after IBM announced its support of the National Geographic's Genographic Project.

History

Early years

Genographic Project IBM's history dates back decades before the development of electronic computers – before that it developed punched card data processing equipment. It originated as the Computing Tabulating Recording (CTR) Corporation, which was incorporated on June 15, 1911 in Binghamton, New York. This company was a merger of the Tabulating Machine Corporation, the Computing Scale Corporation and the International Time Recording Company. The president of the Tabulating Machine Corporation at that time was Herman Hollerith, who had founded the company in 1896. Thomas J. Watson Sr., the founder of IBM, became General Manager of CTR in 1914 and President in 1915. In 1917, the Computing-Tabulating-Recording Company entered the Canadian market under the name of International Business Machines Co., Limited. On February 14, 1924, CTR changed its name to International Business Machines Corporation. The companies that merged to form CTR manufactured a wide range of products, including employee time keeping systems, weighing scales, automatic meat slicers, and most importantly for the development of the computer, punched card equipment. Over time CTR came to focus purely on the punched card business, and ceased its involvement in the other activities.

World War II

During World War II, IBM's German subsidiary Dehomag (a portmanteau formed from "Deutsche Hollerith Maschinen Gesellschaft mbH", translated as "German Hollerith Machine Company Ltd.") provided the Nazi regime with punch card machines. Dehomag was taken over by the Nazis in December 1941. In 2001 author Edwin Black published a book titled [http://www.ibmandtheholocaust.com/ IBM and the Holocaust], which alleged that Thomas J. Watson knew of the German regime's activities and was indifferent to any moral issues. The credibility of Black's book [http://www.businessweek.com/magazine/content/01_12/b3724036.htm has been questioned], as has its claim that the Holocaust would have been impossible without Dehomag's data processing systems. The author [http://www.businessweek.com/magazine/content/01_14/c3726027.htm#B3726028 has responded to these claims]. As of 2004 IBM's possible complicity in the Holocaust is the subject of [http://www.cnn.com/2004/LAW/07/08/ramasastry.holocaust.ibm/ at least one unresolved lawsuit]. IBM has donated more than 10,000 pages of archived documents concerning Dehomag to Hohenheim University in Germany and New York University. The topic is explored in the 2003 documentary film The Corporation. IBM contributed to the war effort by manufacturing the Browning Automatic Rifle and the M1 Carbine.

Airforce and airline projects

In the 1950s, IBM became a chief contractor for developing computers for the United States Air Force's automated defense systems. Working on the SAGE anti-aircraft system, IBM gained access to crucial research being done at MIT, working on the first real-time, digital computer (which included many other advancements such as an integrated video display, magnetic core memory, light guns, the first effective algebraic computer language, analog-to-digital and digital-to-analog conversion techniques, digital data transmission over telephone lines, duplexing, multiprocessing, and networks). IBM built fifty-six SAGE computers at the price of $30 million each, and at the peak of the project devoted more than 7,000 employees (20% of its then workforce) to the project. More valuable to the company in the long run than the profits, however, was the access to cutting-edge research into digital computers being done under military auspices. IBM neglected, however, to gain an even more dominant role in the nascent industry by allowing the RAND Corporation to take over the job of programming the new computers, because, according to one project participant (Robert P. Crago), "we couldn't imagine where we could absorb two thousand programmers at IBM when this job would be over someday." IBM would use its experience designing massive, integrated real-time networks with SAGE to design its SABRE airline reservation system, which met with much success.

Successes of the 1960's

IBM was the largest of the eight major computer companies (with UNIVAC, Burroughs, Scientific Data Systems, Control Data Corporation, General Electric, RCA and Honeywell) through most of the 1960s. People in this business would talk of "IBM and the seven dwarfs", given the much smaller size of the other companies or of their computer divisions. When only Burroughs, Univac, NCR and Honeywell produced mainframes, a bit later, people talked of "IBM and the B.U.N.C.H.". Most of those companies are now long gone as IBM competitors, except for Unisys, which is the result of multiple mergers that included UNIVAC and Burroughs. NCR and Honeywell dropped out of the general mainframe and mini sector and concentrated on lucrative niche markets. General Electric remains one of the world's largest companies, but no longer operates in the computer market. The IBM computer range that earned it its position in the market at that time is still growing today. It was originally known as the IBM System/360 and, in far more modern 64-bit form, is now known as the IBM zSeries (often referred to as "IBM mainframes"). IBM's success in the mid-1960s led to inquiries as to IBM antitrust violations by the U.S. Department of Justice, which filed a complaint for the case U.S. v. IBM in the United States District Court for the Southern District of New York, on January 17, 1969. The suit alleged that IBM violated the Section 2 of the Sherman Act by monopolizing or attempting to monopolize the general purpose electronic digital computer system market, specifically computers designed primarily for business. Litigation continued until 1983, and had a significant impact on the company's practices.

Recent history

On January 19, 1993 Cassandre announced a USD4.97 billion loss for 1992, which was at that time the largest single-year corporate loss in United States history. Since that loss, IBM has made major changes in its business activities, shifting its focus significantly away from components and hardware and towards software and services. In 2004, IBM announced the proposed sale of its PC business to Chinese computer maker Lenovo, which is partially owned by the Chinese government, for USD650 million in cash and USD600 million in Lenovo stock. The deal was approved by the Committee on Foreign Investment in the United States in March 2005, and completed in May 2005. IBM will have a 19% stake in Lenovo, which will move its headquarters to New York State and appoint an IBM executive as its chief executive officer. The company will retain the right to use certain IBM brand names for an initial period of five years.

Facts and trivia

Committee on Foreign Investment in the United States
- The IBM Logo was designed by Paul Rand.
- IBM's Software Group, if it were a separate entity, would be the second largest software company in the world, behind only Microsoft in total revenue. Software Group groups its products into five brands: DB2 (information management), Rational (software development lifecycle), Lotus (collaboration), Tivoli (systems management and security) and WebSphere (application as well as data integration and middleware).
- IBM invented many of the core technologies used in all forms of computing, including the first hard disk drive and the Winchester hard disk drive, the cursor (on computer screens), Dynamic RAM (DRAM), the relational database, Thin Film recording heads, RISC architecture, and the floppy disk. While the floppy disk is rapidly falling into disuse, the infamous Control-Alt-Delete keystroke (David Bradley, 2001: "I invented it, but it was Bill [Gates] that made it famous"), also invented at IBM, is still frequently used on PCs running Windows operating systems.
- The first black employee was hired in 1899 by the Computing Scale Corporation (as it was known at the time).
- IBM began hiring women to work as professional systems service staff in 1935. Thomas J. Watson Sr. wrote: "Men and women will do the same kind of work for equal pay. They will have the same treatment, the same responsibilities and the same opportunities for advancement."
- From 1933 to 1944, IBM punch card machines were installed at various German concentration camps. It has been alleged by a journalist that IBM president Thomas J. Watson, Sr. was aware of their use. Note however that concentration camps are a perfectly legal war disposition regulated by the Geneva convention. The problem lies with extermination camps, about which there were already a lot of war rumours, but nothing that could be confirmed or inferred formally before their discovery by allies in 1945. [http://ibmandtheholocaust.com/]
- From 1942 to 1944 IBM was one of nine companies contracted by the U.S. Government to produce M1 Carbine rifles; these are now sought-after antiques.
- IBM also made clocks until they sold their time division in 1958.
- In 1944, IBM was the first corporation to support the United Negro College Fund.
- In 1953, IBM published the first U.S. corporate mandate on equal employment opportunity, stating that the company would hire people based on their ability, "regardless of race, color or creed". Sexual orientation was added to the nondiscrimination policy in 1984. Genetic makeup was added in 2005.
- IBM invented the USB flash drive in 1998 but did not patent it.
- Whilst IBM did not invent the personal computer, architectures cloned from its design for the IBM PC (which relied on third-party componentry) became the industry standard, and are now often simply called the PC. The IBM PC was introduced on August 12 1981; Microsoft and Intel became monopoly suppliers of two of the key components of PC-compatible systems. IBM agreed to sell its PC division to Lenovo in December 2004 and, when the sale is complete, will come out of the business of manufacturing / designing / selling PCs, the business which it created in 1981.
- The IBM iSeries minicomputer (in its 24-year history also variously known as i5, AS/400 and System/38) is the world's largest-selling computer family, if PC-type machines are excluded. It was the first successful 64-bit machine. It has been calculated that, if the Rochester, Minnesota facility that produces the machine were independent, it would be the third largest computer company in the world.
- In 2004, for the twelfth consecutive year, IBM was awarded the greatest number of patents by the USPTO. IBM received 3,248 patents that year. (Reference: [http://www.uspto.gov/web/offices/com/speeches/05-03.htm USPTO Releases Annual List of Top 10 Organizations Receiving Most U.S. Patents])

Acquisitions

- 1889 Bundy Manufacturing Company incorporated.
- 1891 Computing Scale Company incorporated.
- 1893 Dey Patents Company (Dey Time Registers) incorporated.
- 1894 Willard & Frick Manufacturing Company (Rochester, New York) incorporated.
- 1896 Detroit Automatic Scale Company incorporated.
- 1896 Tabulating Machine Company incorporated.
- 1899 Standard Time Stamp Company acquired by Bundy Manufacturing Company.
- 1900 Willard & Frick Manufacturing Company (Rochester) acquired by International Time Recording Company.
- 1901 Chicago Time-Register Company acquire by International Time Recording Company.
- 1901 Dayton Moneyweight Scale Company acquire by Computing Scale Company.
- 1901 Detroit Automatic Scale Company acquired by Computing Scale Company.
- 1902 Bundy Manufacturing Company acquired by International Time Recording Company.
- 1907 Dey Time Registers acquired by International Time Recording Company.
- 1908 Syracuse Time Recording Company acquired by International Time Recording Company.
- 1911 Computing Scale Company acquired by Computing-Tabulating-Recording Company (C-T-R).
- 1911 International Time Recording Company acquired by Computing-Time-Recording Company (C-T-R).
- 1911 Tabulating Machine Company acquired by Computing-Tabulating-Recording Company (C-T-R).
- 1917 American Automatic Scale Company acquired by Computing-Tabulating-Recording Company (C-T-R) as International Scale Company.
- 1917 C-T-R opens in Canada as IBM.
- 1921 Pierce Accounting Machine Company (asset purchase).
- 1921 Ticketograph Company (of Chicago).
- 1924 C-T-R renamed IBM.
- 1930 Automatic Accounting Scale Company.
- 1932 National Counting Scale Company.
- 1933 Electromatic Typewriters Inc. (See: IBM Electromatic typewriter)
- 1941 Munitions Manufacturing Corporation.
- August, 1959 Pierce Wire Recorder Corporation.
- 1984 ROLM.
- 1986 RealCom Communications Corporation.
- 1995 Lotus Development Corporation for $3.5 billion.
- 1996 Tivoli Systems for $743 million.
- 1997 Software Artistry for $200 million.
- 1997 Unison Software.
- 1998 CommQuest Technologies.
- 1999 Mylex Corporation.
- 1999 Sequent Computer Systems for $810 million.
- 2001 Informix Software (a purchase of assets rather than a true acquisition) for $1.0 billion.
- 2001 Mainspring Inc. for $80 million.
- January, 2002 Crossworlds.
- 2002 PricewaterhouseCoopers' Consulting for $3.5 billion (recalculated by IBM in August 2003 as $3.9 billion).
- October, 2003 CrossAccess.
- 2003 Rational Software Corporation for $2.1 billion.
- 2003 Presence Online, Aptrix. July.
- 2004 Maersk Data & DMData.
- March, 2004 Logicalis Australia (renamed to [http://www.cerulean.com.au Cerulean Solutions] in April 2005) and Logical CSI New Zealand.
- April, 2004 Candle Corp., Daksh eServices in India.
- July, 2004 Alphablox.
- July, 2004 Cyanea Systems.
- August, 2004 Venetica.
- October, 2004 Systemcorp.
- February 2005 Corio crio for $211 million.
- April 2005 Ascential Software for approximately $1.1 billion in cash.
- May 2005 Gluecode.
- July 2005 PureEdge.
- August, 2005 DWL.
- October, 2005 DataPower.

Spinoffs

- 1934 Dayton Scale Division is sold to the Hobart Manufacturing Company.
- 1942 Ticketograph Division is sold to the National Postal Meter Company.
- 1958 Time Equipment Division is sold to the Simplex Time Recorder Company.
- Taligent, a joint software venture with Apple Computer.
- Prodigy, formerly a joint venture with Sears.
- [http://www.attbusiness.net AT&T Business Internet], formerly IBM Global Network, formerly Advantis (joint venture with Sears).
- ARDIS mobile packet network, a joint venture with Motorola. Now [http://www.motient.com Motient].
- 1991 Lexmark (keyboards, typewriters, and printers). IBM Retained a 10% interest. Lexmark has sold its keyboard and typewriter businesses. [http://www.printers.ibm.com IBM Printing Systems] now competes with Lexmark.
- 1996 [http://www.celestica.com/ Celestica] Electronic Manufacturing Services (EMS).
- 2003 [http://www.hitachigst.com Hitachi Global Storage Technologies] now provides many of the hardware storage devices formerly provided by IBM, including IBM Harddrives & The Microdrive. IBM continues to develop [http://ibm.com/storage storage systems], including Tape Backup, Storage software, Enterprise storage, etc.
- December, 2004 Lenovo acquires 90% interest in IBM Personal Systems Group, 10,000 employees and $9 billion in revenue.

Projects

BlueEyes

BlueEyes is the name of a human recognition venture initiated by IBM to allow people to interact with computers in a more natural manner. The technology aims to enable devices to recognize and use natural input, such as facial expressions. The initial developments of this project include scroll mice and other input devices that sense the user's pulse, monitor his or her facial expressions, and the movement of his or her eyelids.

alphaWorks

Free software available at [http://alphaWorks.ibm.com/ alphaWorks] (IBM's showcase for emerging software technology): #Flexible Internet Evaluation Report Architecture: A highly flexible architecture for the design, display, and reporting of Internet surveys. #History Flow Visualization Application: A tool for visualizing dynamic, evolving documents and the interactions of multiple collaborating authors. Examples from Wikipedia. [http://www.alphaworks.ibm.com/screenshots/16E98A61CB7178D488256FC70075E6CD/$FILE/historyflow01.jpg] [http://www.alphaworks.ibm.com/screenshots/4985F7ED629EE82D88256FC700764E11/$FILE/historyflow03.jpg] #IBM Performance Simulator for Linux on POWER: A tool that provides users of Linux on Power a set of performance models for IBM's POWER processors. #Database File Archive And Restoration Management: An application for archiving and restoring hard disk files whose file references are stored in a database. #Policy Management for Autonomic Computing: A policy-based autonomic management infrastructure that simplifies the automation of IT and business processes. (This is an ETTK technology.) #FairUCE: A spam filter that stops spam by verifying sender identity instead of filtering content. #Unstructured Information Management Architecture (UIMA) SDK: A Java SDK that supports the implementation, composition, and deployment of applications working with unstructured information. [http://www.alphaworks.ibm.com/tech/uima]

Gaming Chips

IBM has also been developing processing chips for gaming consoles. The new Xbox 360 contains IBM's new tri-core chipset, which at the request of Microsoft IBM was able to design and ramp up to production volumes in less than 24 months (albeit using contract manufacturing). Meanwhile, Sony's PlayStation 3 will feature the Cell, a new chip designed by IBM, Toshiba and Sony in a joint venture. (Toshiba plans to use it on HD TVs). It has been reported that the Nintendo Revolution will also feature an IBM chip, like the Revoloution's predecessor, Nintendo Gamecube.

Corporate governance

Current members of the board of directors of IBM are: Cathleen Black, Ken Chenault, Juergen Dormann, Michael Eskew, Shirley Ann Jackson, Charles F. Knight, Minoru Makihara, Lucio Noto, Samuel Palmisano, Joan Spero, Sidney Taurel, Charles Vest, and Lorenzo Zambrano.

References

- Gerstner, Jr., Louis V. (2002). Who Says Elephants Can't Dance? HarperCollins. ISBN 0-00-715448-8.

External links

- [http://www.ibm.com/ Company home page]
- [http://www.ibm.com/ondemand IBM On Demand Business home page]
- [http://www.ibmtechnology.com/ IBM Technology]
- [http://www-1.ibm.com/servers/ IBM eServer].
- [http://www.ibm.com/ibm/history/ History and Archives]
- [http://barry_froggatt.users.btopenworld.com/songbook.html The IBM Songbook]; [http://anthems.zdnet.co.uk/anthems/ibm.swf Ever Onward] (needs Flash)
- [http://www.research.ibm.com/ IBM Research]
- [http://www.research.ibm.com/cambridge IBM Research in Cambridge, Massachusetts]
- [http://www.research.ibm.com/history/ IBM Research specific to Wikipedia.org]
- [http://www.zurich.ibm.com IBM Research in Zurich]
- [http://www.hagley.lib.de.us/1980.htm IBM Antitrust Suit Records 1950-1982]
- [http://tuxmobil.org/ibm.html Linux on IBM laptops]
- [http://www.google.com/search?q=ibmjarg IBM Jargon Dictionary]
- [http://www.ibm.com/ibm/sjp/ Current CEO - Samuel J Palmisano]
- [http://www.almaden.ibm.com/cs/BlueEyes/index.html BlueEyes Project Description]
- [http://www.computercraft.com/docs/ibm.html IBM Compatibles]
- [http://ibm.com/developerworks/ developerWorks - IBM's resource for software developers]
- [http://www-128.ibm.com/developerworks/blogs/index.jspa developerWorks blogging community]
- [http://ibm.com/alphaworks alphaWorks - IBM's showcase for emerging technology]
- [http://www.power.org power.org]
- [http://www.ibmtechnology.net/ Ibm technology NET] Category:Electronics companies Category:IBM Category:Fortune 500 companies ko:아이비엠 ja:IBM th:ไอบีเอ็ม

Backronym

A backronym or bacronym is a type of acronym that is formed to match the letters of a word already in use. The word "backronym" is a portmanteau of back and acronym and was coined in 1983. An acronym involves a phrase being reduced to a set of initials which can then be pronounced as a word: North Atlantic Treaty Organisation becomes NATO. A backronym is the phenomenon that the short word exists first and is then expanded to a phrase. There are both official (and generally serious), as well as unofficial (and often humorous) backronyms. When a backronym is peddled as the origin of a word, it is often an example of false etymology; when it is widely believed it may have the status of a folk etymology, but more usually it is intended and understood as a joke, in which case it would be classed as an example of fake etymology. A pure backronym occurs when a sequence of letters is commonly understood to stand for a phrase that in fact had no role in its original conception. An example is SOS, the international distress signal that was chosen solely for its easy recognizability in Morse code, but which is often thought to stand for "save our ship", "save our souls" or something similar. An older distress signal, CQD, also has a backronym: "come quick, distress (or danger)." Another example is the word "wiki", from the Hawaiian word meaning quick. Since its application to consumer generated media, some have suggested that wiki means, "What I Know Is." Some backronyms are back-formed by replacing one word in an acronym with another, when the original meaning is deemed obsolete or inaccurate. DVD, for example, was originally an acronym for "digital video disc"; when it was realized that a DVD could be used for non-video applications, the term "digital versatile disc" was invented (although it did not become official, since the official meaning behind DVD is nothing at all, i.e. it doesn't stand for anything in particular). [http://www.dvddemystified.com/dvdfaq.html#1.1] Another example is GSM, which originally started as an acronym for a French research group called "Groupe Spécial Mobile", but was later modified to stand for Global System for Mobile Communications. A well-known example in the United States is the SAT, which originally stood for "Scholastic Aptitude Test" but was changed to "Scholastic Assessment Test" after parent groups complained that the word "aptitude" implied that test scores reflected only innate talent and not preparation. SAP originally stood for Spanish Audio Program, but eventually came to be described as Secondary Audio Program. Other backronyms are back-formed from an existing word that was not previously an acronym. Generally these 'backronyms' are apronyms, as the word used as the 'backronym' is relevant to the expanded term it stands for. The relevance may be either serious or ironic. Most apronyms are examples of 'backronyms'. An example of this is the word acronym itself which can be A Clever Representation Of Names You Manufacture. Many jocular (and often also derogatory) apronyms are created as a form of wordplay. Example is the former name for PC Card, PCMCIA: People Cannot Memorize Computer Industry Acronyms (for Personal Computer Memory Card Industry Association). There are also false backronyms, in which letters are commonly, but inaccurately, thought to represent a phrase. An example is A.D., which stands for Anno Domini (Latin: "in the year of the Lord") and counts years since the birth of Jesus. However, many people incorrectly interpret its definition as 'After Death [of Christ]'. Another is R.I.P, which is actually an internationally-used acronym for Latin Requiescat in pace, not an English acronym for "Rest in Peace", as often thought, although the Latin and the English phrases have similar meaning and the same initials. Also, R.P.G. is commonly thought to stand for "Rocket-Propelled Grenade", but actually stands for a Russian phrase meaning "handheld antitank grenade-launcher". Some 'backronyms' are recursive acronyms like GNU, PHP or the pseudo-acronym JINI.

External links

- [http://www.acronymfinder.com/af-query.asp?Acronym=acronym Backronym expansions of ACRONYM (Acronym Finder)]
- [http://www.wordspy.com/words/bacronym.asp Citations of the word "backronym"] from The Word Spy Category:Acronyms Category:Neologisms Category:Portmanteaus

PowerPC

PowerPC is a RISC microprocessor architecture created by the 1991 Apple-IBM-Motorola alliance, known as AIM. Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors as well. PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform initiatives in the 1990s, but the architecture found the most success in the personal computer market in Apple's Power Macintosh line from 1994-2005. PowerPC is largely based on IBM's earlier POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation.

History

operating systemThe history of the PowerPC begins with IBM's 801 prototype chip of John Cocke's RISC ideas in the late '70s. 801-based cores were used in a number of IBM embedded products, eventually becoming the 16-register ROMP processor used in the IBM RT. The RT had disappointing performance and IBM started the America Project to build the fastest processor on the market. The result was the POWER architecture, introduced with the RISC System/6000 in early 1990. The original POWER microprocessor, one of the first superscalar RISC implementations, was a high performance, multi-chip design. IBM soon realized that they would need a single-chip microprocessor and to eliminate some POWER processor instructions to scale their RS/6000 line from lower-end to high-end machines, and work on a single-chip POWER microprocessor began. In early 1991 IBM realized that their design could potentially become a high-volume microprocessor used across the industry. IBM approached Apple with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture. Soon after, Apple, as one of Motorola's largest customers of desktop-class microprocessors, asked Motorola to join the discussions because of their long relationship, their more extensive experience with manufacturing high-volume microprocessors than IBM and to serve as a second source for the microprocessors. This three-way collaboration became known as AIM alliance, for Apple, IBM, Motorola. To Motorola, POWER looked like an unbelievable deal. It allowed them to sell a widely tested and powerful RISC CPU for little design cash on their own part. It also maintained ties with an important customer, Apple, and seemed to offer the possibility of adding another in IBM who might buy smaller versions from them instead of making their own. At this point Motorola already had its own RISC design in the form of the 88000 which was doing poorly in the market. A likely reason was that the Motorola chips were consistently late to market due to poor design methodology and manufacturing issues, so late they lost their window of opportunity to be viable competitors to designs like the MIPS and SPARC which beat the 88000 to market. However, the 88000 was already in production; Data General was shipping 88k machines and Apple already had 88k prototype machines running. If the new POWER single-chip solution could be made bus-comparable at a hardware level with the 88000, that would allow both Apple and Motorola to bring machines to market much faster since they would not have to redesign their board architecture. The result of these various requirements was the PowerPC (Performance Computing) specification. Everyone seems to have won:
- IBM got the single-chip CPU they were looking for
- Apple got to use one of the most powerful RISC CPUs on the market, and massive press buzz due to IBM's name
- Motorola got an up-to-date RISC chip, and help with design methodology from IBM When the first PowerPC products reached the market, they were met with enthusiasm. In addition to Apple, both IBM and the Motorola Computer Group offered systems built around the processors. Microsoft created a version of Windows NT for the architecture, which was used in Motorola's PowerPC servers, and Sun Microsystems offered a version of its Solaris OS. IBM ported its AIX Unix and planned a release of OS/2. Throughout the mid-1990s, PowerPC processors achieved Benchmark test scores that matched or exceeded those of the fastest x86 CPUs. Ultimately, demand for the new architecture on the desktop never truly materialized. Windows, OS/2 and Sun customers, faced with the lack of application software for the PowerPC, almost universally ignored the chip. The PowerPC versions of Solaris, OS/2, and Windows were discontinued after only a brief period on the market. Only on the Macintosh, due to Apple's persistence, did the PowerPC gain traction. To Apple, the performance of the PowerPC was a bright spot in the face of increased competition from Windows 95 and Windows NT-based PCs. However, toward the close of the decade, the same manufacturing issues began plaguing the AIM alliance in much the same way it did Motorola with consistently pushed back deployments of new processors for Apple and other vendors: first from Motorola in the 1990s with the G3 and G4 processors, and IBM with the 64-bit G5 processor in 2003. In 2004, Motorola exited the chip manufacturing business by spinning off its processor business as an independent company called Freescale Semiconductor. Around the same time, IBM exited the personal computer market completely by selling its line of PC products (which used Intel processors) to Chinese computer manufacturer Lenovo and focused their chip designs for PowerPC CPUs towards game machine makers such as the Nintendo Revolution, Sony's Playstation 3 and Microsoft's Xbox 360. In 2005 Apple announced they would no longer use PowerPC processors in their Apple Macintosh computers, favoring Intel produced processors instead, citing the performance limitations of the chip for future personal computer hardware specifically related to heat generation and energy usage in future products, as well as the inability of IBM to move the 970 (PowerPC G5) processor to the 3 GHz range. This was considered a public relations problem for IBM, since the decision was made in part by their inability to match Intel and other competitors in terms of speed and architecture improvements. This effectively ended the AIM alliance with IBM continuing to use and evolve the PowerPC processor on game consoles and Freescale Semiconductor focusing solely on embedded devices. This left the future of the PowerPC platform on anything other than embedded devices in much doubt. However, the original POWER architecture IBM developed and from which the PowerPC processor was originally derived was still very much alive on their server offerings for large businesses and continues to evolve to this day.

Design features

The PowerPC is designed along RISC principles, and allows for a superscalar implementation. Versions of the design exist in both 32-bit and 64-bit implementations. Starting with the basic POWER specification, the PowerPC added:
- Support for operation as in both big-endian and little-endian modes; the PowerPC can switch from one mode to the other at run-time (see below). This feature is not supported in the PowerPC G5. (This was the reason why Virtual PC took so long to be made functional on G5-based Macintoshes.)
- Single-precision forms of some floating point instructions, in addition to double-precision forms
- Additional floating point instructions at the behest of Apple
- A complete 64-bit specification, which is backward compatible with the 32-bit mode
- Removal of some of the more esoteric POWER instructions, some of which could be emulated by the operating system if necessary.

Endian-modes

In Little-Endian mode, the three lowest-order bits of the effective address are exclusive-ORed with a three bit value selected by the length of the operand. This is not quite the same as being truly little-endian, and can cause problems when communicating with external devices. In theory the byte order of the processor can be switched at run-time to support both Big- and Little-Endian programs simultaneously, and in fact it is possible to run a program in one mode and exception handlers (in other words, the operating system) in another. Practically speaking this would be difficult due to the interaction with external devices which have their own byte ordering. An interesting side-effect of this implementation is that a program can store a 64-bit value (the longest operand format) to an address A while in one endian mode, switch modes, and when the value is read back from A it will be identical, even though ostensibly the processor is now in the opposite byte order mode.

Implementations and design wins

The first single-chip implementation of the design was the MPC601, a hybrid of the POWER1 and PowerPC specifications released in 1992. This allowed the chip to be used by IBM in their existing POWER1 based platforms, although it also meant some slight pain when switching to the 2nd generation "pure" PowerPC designs. Apple continued work on a new line of Macintosh computers based on the chip, and eventually released them as the 601-based Power Macintosh on March 14, 1994. IBM also had a full line of PowerPC based desktops built and ready to ship; unfortunately, the operating system which IBM had intended to run on these desktops—Microsoft Windows NT—was not complete by early 1993, when the machines were ready for marketing. Accordingly, and further because IBM had developed animosity toward Microsoft, IBM decided to rewrite OS/2 for the PowerPC. It took IBM two years to rewrite OS/2 for PowerPC, and by the time the operating system was ready, the market for OS/2 on PowerPC had evaporated. For this reason, the IBM PowerPC desktops did not ship, although the reference design (codenamed Sandalbow) based on the PowerPC 601 CPU was released as an RS/6000 model (Byte magazine 's April 1994 issue included an extensive article about the Apple and IBM PowerPC desktops). Apple, who also lacked a PowerPC based OS, took a different route. They rewrote the essential pieces of their Mac OS operating system for the PowerPC architecture, and further wrote a 680x0 emulator which could run the remaining parts of the unrewritten OS and 68K based applications. The second generation was "pure" and included the "low end" 603 and "high end" 604. The 603 is notable due to its very low cost and power consumption. This was a deliberate design goal on Motorola's part, who used the 603 project to build the basic core for all future generations of PPC chips. Apple tried to use the 603 in a new laptop design but was unable to due to the small 8KB level 1 cache. The 68000 emulator in the Mac OS could not fit in 8KB and thus slowed the computer drastically. The 603e solved this problem by having a 16KB L1 cache which allowed the emulator to run efficiently. In 1993, developers at IBM's Burlington, Vermont facility started to work on a version of the PowerPC that would support the Intel x86 instruction set directly on the CPU. While the work was done by IBM without the support of the AIM alliance, this chip began to be known inside IBM and by the media as the PowerPC 615. However, profitability concerns and performance issues in the switching between the x86 and native PowerPC instruction sets resulted in the project being canceled in 1995 after only a limited number of chips were produced for in-house testing.[http://www.theregister.co.uk/1998/10/01/microsoft_killed_the_powerpc/] The first 64-bit implementation was the 620, but it appears to have seen little use since Apple didn't want to buy it and with its large die area, was too expensive for the embedded market. It was later and slower than promised, and IBM used their own POWER3 design instead, offering no 64-bit "small" solution until the late-2002 introduction of the PowerPC 970. The 970 is a 64-bit processor derived from the POWER4 server processor. To create it, the POWER4 core was modified to be backwards-compatible with 32-bit PowerPC processors, and a vector unit (similar to the AltiVec extensions in Motorola's 74xx series) was added. IBM's RS64 family is a modified PowerPC architecture. These processors are used in the RS/6000 and AS/400 computer families. Numerically, the PowerPC is mostly found in controllers in cars. In this role, Freescale Semiconductor has offered up a huge number of versions called the MPC5xx family such as the MPC555, built on a variant of the 601 core called the 8xx designed in Israel by MSIL (Motorola Silicon Israel Limited). The 601 core is single issue, meaning it can only issue one instruction in a clock cycle. To this they add various bits of custom hardware, to allow for I/O on the single chip. Networking is another area where embedded PowerPC processors are found in large numbers. MSIL took the QUICC engine from the MC68302 and made the PowerQUICC MPC860. This was a very famous processor used in many Cisco edge routers in the late 1990s. Variants of the PowerQUICC include the MPC850, and the MPC823/MPC823e. All variants include a separate RISC microengine called the CPM that offloads communications processing tasks from the central processor and has functions for DMA. The follow-on chip from this family, the MPC8260, has a 603e-based core and a different CPM. Operating systems used in PowerPC systems include the LynxOS real-time operating system and BlueCat embedded Linux from LynuxWorks.

Design win summary

PowerPC processors have been used in many products, among which are the following: Apple Macintosh post-68k models (called PowerMacs), IBM RS/6000 UNIX workstations, Cisco routers, Amiga post-68k models (called the AmigaOne), Amiga "Classic" accelerator boards, Pegasos, the Nintendo GameCube video game console, and many embedded systems such as the TiVo personal video recorder. PowerPC-based CPU upgrades for use in Macintosh systems are manufactured by Sonnet Technologies, Daystar and previously by Newer Technology which once lead the industry. In 2003, NASA launched two Mars rovers (Spirit and Opportunity) that used PowerPC processors; essentially a harsh environment-resistant 604e. All three of the major game console manufacturers have announced that their sixth-generation consoles will contain PowerPC-based processors:
- Sony's PlayStation 3 console, to be released in spring 2006, will contain a Cell processor, containing a 3.2 GHz PowerPC control processor, with eight 3.2 GHz closely-coupled DSP-like accelerator processors, seven active and one spare.
- Microsoft's Xbox 360 console, to be available from the 2005 holiday season, includes a 3.2 GHz custom IBM PowerPC chip with three symmetrical cores.
- The Nintendo Revolution console, predicted to ship some time in 2006, is billed as containing a PowerPC-based processor, but technical details have yet to be released.

General-purpose PowerPC processors

PowerPC processors bring the processor's local bus to the chip's surface, and connect to a bridge chip that translate this into other on-board device buses that attach to RAM, PCI, and other devices.
- 601 MPC601 50 and 66 MHz
- 602 consumer products (multiplexed data/address bus)
- 603 notebooks
- 603e
- 604
- 604e
- 620 the first 64-bit implementation
- x704 BiCOMOS PowerPC implementation by Exponential Technologies
- 750 (PowerPC G3) (1997) 233 MHz and 266 MHz, 740, 745, 755
- 7400 (PowerPC G4) (1999) 350 MHz, 7410 uses AltiVec, a SIMD extension of the original PPC specs
- 750FX announced by IBM in 2001 and available early 2002 at 1 GHz
- 7450 microarchitecture family
- 970 (PowerPC G5) (2003) A 64-bit implementation derived from the IBM POWER4 enhanced with VMX (AltiVec compatible SIMD extensions) operating at speeds of 1.4 GHz, 1.6 GHz, 1.8 GHz, 1.9 GHz, 2.0 GHz, 2.1 GHz, 2.3 GHz, 2.5 GHz and 2.7 GHz
- Gekko 485 MHz (used in the Nintendo GameCube)
- PA6T-1682M (PWRficient): a dual core PPC running at 2 GHz

Embedded PowerPC microcontrollers

32-bit PowerPC processors have been a favorite of embedded computer designers. To keep costs low on high-volume competitive products, the CPU core is usually bundled into a system-on-chip (SOC) integrated circuit. SOCs contain the processor core, cache and the processor's local data on-chip, along with clocking, timers, memory (SDRAM), peripheral (network, serial I/O), and bus (PCI, PCI-X, ROM/Flash bus, I2C) controllers. IBM also offers an open bus architecture (called CoreConnect) to facilitate connection of the processor core to memory and peripherals in a SOC design. IBM and Motorola have competed along parallel development lines in overlapping markets. A recent development is the BookE PowerPC Specification, implemented by both IBM and Freescale Semiconductor, which defines embedded extensions to the PowerPC programming model.

IBM (now from AMCC)

- 401
- 403: MMU added in most advanced version 403GCX
- 405: MMU, Ethernet, serial, PCI, SRAM, SDRAM; NPe405 adds more network devices
- 440xx: A range of processors based on the Book E core.
- 440EP: 333-667 MHz, (2) 10/100 Ethernet, PCI, DDR, FPU, USB 1.1 & 2.0, 32k L1 Cache.
- 440GP: 400-500 MHz, (2) 10/100 Ethernet, PCI-X, DDR, 32k L1 Cache.
- 440GX: 533-800 MHz, (2) 10/100 Ethernet, (2) 10/100/1G Ethernet with TCP/IP hardware acceleration, PCI-X, DDR, 32k L1 Cache

AMCC

- 440SP: 533-667 MHz, 10/100/1G Ethernet, (2) 64bit PCI-X, 32bit PCI-X, XOR engine, 32k L1 Cache.
- 440SPe: 533-667 MHz, 10/100/1G Ethernet, (3) 64bit PCI-Express, 64bit PCI-X, XOR engine, 32k L1 Cache.
- 440EPx: 333-667 MHz, (2) 10/100/1G Ethernet, Hardware Security, PCI, DDR-II, FPU, USB 2.0, 32k L1 Cache.
- 440GR: 333-667 MHz, (2) 10/100 Ethernet, (4) UART, (2) IIC, 53 GPIO, SPI, 32k L1 Cache.
- 440GRx: 333-667 MHz, (2) 10/100/1G Ethernet, (4) UART, (2) IIC, 53 GPIO, SPI, DDR-II, Hardware Security, 32k L1 Cache.

Motorola (now Freescale Semiconductor)

- MPC 860/8xx (PowerQUICC): networking & telecomm card controllers
- MPC 550/5xx line: (8xx core) automotive & industrial controllers
- MPC 5200/5200B (603e core) automotive & industrial controllers
- MPC 8260/82xx (PowerQUICC II) a 603 core, networking & telecomm system controllers with high-capacity onchip switched bus
- MPC 8560/85xx (PowerQUICC III) a PowerPC Book E core, networking & telecomm system controllers with even higher-capacity onchip

PA Semi

- PA6T-1682M (PWRficient): a dual core PPC running at 2 GHz (unreleased)

References

- May, Cathy (editor) et.al. (1994). The PowerPC Architecture: A Specification for A New Family of RISC Processors. Morgan Kaufmann Publishers. ISBN 1-55860-316-6 (2nd ed.).
- Hoxey, Steve (editor) et.al. The PowerPC Compiler Writer's Guide. Warthman Associates. ISBN 0-9649654-0-2.
- Motorola. Programming Environments Manual for 32-bit Implementations of the PowerPC Architecture. P/N MPCFPE32B/AD .
- IBM (2000). Book E: Enhanced PowerPC™ Architecture (3rd ed.)
- Jeff Duntemann and Ron Pronk. (1994) Inside the PowerPC Revolution. Coriolis Group Books, ISBN 1-883577-04-7

External links

- [http://www-106.ibm.com/developerworks/linux/library/l-powarch/ A developer's guide to the PowerPC architecture]– From IBM Developerworks.
- [http://haxor.dk/articles/ppc.html PowerPC road map at haxor.dk]
- [http://www.cpu-collection.de/?tn=1&l0=cl&l1=PowerPC PowerPC images and descriptions at cpu-collection.de]
- Like all Motorola processors, the PowerPC is produced by what was once Motorola's Semiconductor Products Sector, now spun off into an independent company named Freescale Semiconductor [http://freescale.com/].
- [http://www.power.org Power.org] IBM's Power website
- [http://lowendmac.com/orchard/05/0801.html IBM, Apple, RISC, and the roots of the Power Mac]
- [http://pages.prodigy.net/michaln/history/os2ppc/index.html OS/2 Warp, PowerPC Edition] review by Michael Necasek 2005
- [http://pearpc.sourceforge.net PearPC] - PowerPC architecture emulator
- [http://www.amcc.com/Embedded AMCC Embedded processors]
- [http://www.pasemi.com/ P.A. Semi - Power to Perform]
- [http://www.pegasosforum.de/ Pegasos Forum] - German Community of the Pegasos PowerPC Project Category:PowerPC microprocessors Category:Windows NT ja:PowerPC

Apple Macintosh

The Macintosh, commonly called the Mac for short, is a line of personal computers designed, developed, manufactured and marketed by Apple Computer, running the Macintosh operating system ("Mac OS"). Named after the McIntosh apple, the